CMOS mm-Wave Transmission Lines
Sure, there are a lot of texts out there about the theoretical principles of transmission line design and we won’t repeat them here.
We all know that a transmission line is a two-wire system with a signal and return path and is described in terms of its distributed inductance L’ (H/m), capacitance C’ (F/m), resistance R’ (/m), and conductance G’ (S/m). The complex propagation constant γ = α + jβ, where α is the attenuation constant and β is the phase constant, is used for describing the AC signal propagation. In its general form the complex propagation constant is given by γ =sqrt((R’ + jωL’)(G’ + jωC’)).
But how do you actually design a transmission line to exhibit specific electrical parameters, e.g. characteristic impedance Z~sqrt(L’/C’) and a specific phase constant β~sqrt(L’C’). Well, if you look simply at the formulation you may say… it’s not that hard, design a transmission line with a specific per length inductance L’ and capacitance C’ that fits your specification.
Example of designed 50Ω CMOS Coplanar Waveguide Transmission Line
Absolutely, you’re right, in principle it really all comes down to the per length metrics. The cumbersome part is to understand the transmission line physics and how a certain geometry affects them. E.g. does a microstrip or coplanar waveguide transmission line have similar current return paths?
Take a look at a typical cross section and judge by yourself… a) Microstrip and b) Coplanar Waveguide
Why is a CMOS design that challenging?
Take a look at the simplified cross sections, from left to right, 65nm, 40nm and 28nm CMOS process cross-sections.
Challenge in CMOS design lies with several limitations and constraints that arise from the technology itself. Transmission lines on CMOS are typically fabricated using the upper metals of the back end of line (BEOL) due to their superior conductivity. The BEOL process imposes hard constraints on the size and physical position of those metals, with each layer having specific thickness, conductivity, and height from the silicon substrate. BEOL metals are embedded in silicon oxide dielectrics with relative permittivities typically ranging from 3 to 8. In addition to that, certain design rules limit the minimum and maximum width and minimum spacing of the metal layers, as well as metal density.
As a topping, take this stack-up and embed it in a total of ~ 40 dielectrics 🙂
Wait, no reason to be desperate… this is why I wrote my IEEE MTT Transactions paper entitled Parametric Analysis and Design Guidelines for mm-Wave Transmission Lines in nm CMOS.
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